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Microcomputer Components
Standalone Full-CAN Controller
SAE 81C90/91
Data Sheet 01.97 Preliminary
Stand Alone Full CAN Controller
q Full CAN controller for data rate up to 1 Mbaud q Complies with CAN specification V2.0 part A q q q q q q q q q q
SAE 81C90/91
(part B passive) Up to 16 messages simultaneous (each with maximum data length) Message identifier reprogrammable "on the fly" Several transmit jobs can be sent with a single command Transmit check Basic CAN feature Time stamp for eight messages Two host interfaces (parallel and serial) User-configurable outputs for different bus concepts Programmable clock output Two 8 bit I/O-Port extension (P-LCC-44-1 package only)
P-LCC-44-1
P-LCC-28-1 The device comes in two versions: SAE 81C90 in a P-LCC-44-1 package with two 8-bit l/O ports, and SAE 81C91 in a P-LCC-28-1 package without l/O ports.
SAE 81C90/91 Revision History: Previous Releases: Page 1056 1057 1059 1065 - 1084 1066, 1069 1093 1093 Subjects
Version 01.97 06.95 05.94 (Copy version)
Figure 1 corrected. Figure 2 corrected. Notes updated. Register description and arrangement improved. New register maps. tAVLL, tLLAX, tDVWH changed to 10 ns. tWHDX changed to 5 ns.
Controller Area Network (CAN): License of Robert Bosch GmbH Semiconductor Group 1 01.97
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Introduction The Siemens Stand Alone Full CAN (SFCAN) circuit incorporates all the parts for completely autonomous transmission and reception of messages using the CAN protocol. The flexible, programmable interface allows hookup to different implementations of the physical layer. The link to a host controller can be made either by a multiplexed 8-bit address/data bus or by a high-speed, serial synchronous interface.
Figure 1 Logic Symbol Ordering Information Type SAE 81C91 SAE 81C90 Ordering Code Q67121-F0001 Q67121-H9038 Package P-LCC-28-1 P-LCC-44-1 Function Stand Alone Full CAN Controller Temperature range - 40 to + 110 C Stand Alone Full CAN Controller Temperature range - 40 to + 110 C
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Pin Configurations (top view)
Figure 2
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Pin Definitions and Functions Symbol X1 1) X2 1) CLKOUT 1) RES AD0/DI AD1/DO AD2/CLK AD3/W AD4/TIM AD5 AD6 AD7 RD WR ALE CS INT MS Pin Number 11 10 14 19 42 43 44 1 2 3 4 5 35 36 34 27 41 26 Input (I) PLCC-48 PLCC-28 Output (O) 28 27 3 4 19 20 21 22 23 24 25 26 16 17 15 12 18 11 - - - - 10 9 8 7 5 O I O I I/O I/O I/O I/O I/O I/O I/O I/O I I I I O I I/O I/O I/O I/O O O I I I Function Crystal oscillator output. Must be unconnected for external clock input. Crystal oscillator input. Used for external clock input. Clock output Reset. (Schmitt trigger characteristic) PI: Address / Data bus / SI: Data input PI: Address / Data bus / SI: Data output PI: Address / Data bus / SI: Clock input PI: Address / Data bus / SI: Write select PI: Address / Data bus / SI: TIM = 0: Timing A; TIM = 1: Timing B PI: Address/Data bus PI: Address/Data bus PI: Address/Data bus PI: Read / SI: no Function PI: Write / SI: no Function PI: Address Latch Enable / SI:no Function Chip Select Interrupt Mode Select (PI SI) Port 0 These pins provide internal pullup resistors of about 10...200 k. Port 1 These pins provide internal pullup resistors of about 10...200 k. Transmitter output 0 Transmitter output 1 Comparator input 0 / Digital input 2) Comparator input 1 2) Analog power supply for comparator (may be unconnected using the digital mode)
P00 ... P03, 28, 29, 30, 31, P04 ... P07 37, 38, 39, 40 P10 ... P13, 18, 17, 16, 15, P14 ... P17 9, 8, 7, 6 TX0 TX1 RX0 RX1 25 24 23 22 20
VDDA
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Pin Definitions and Functions (cont'd) Symbol Input (I) PLCC-48 PLCC-28 Output (O) 21 13 32 12 33 6 2 13 1 14 I I I I I Pin Number Function Analog power ground for comparator (must always be connected) Digital power supply 3) Digital power supply Digital power ground 3) Digital power ground
VSSA VDD1 VDD2 VSS1 VSS2
1)
For best results keep the crystal circuitry connections as short as possible and keep the CLKOUT line away from it. If the bus lines work according to the ISO specification, additional circuitry is necessary for interconnection of the input comparator to the bus lines. The digital mode is enabled by setting bit DI in register BL2. When using the digital mode pin RX1 should be on VSS. It is recommended to decouple these supply pins close to the device using a 10 pF capacitor in addition to the standard 100 nF capacitor.
2)
3)
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Functional Description The Siemens stand-alone Full-CAN (SFCAN) circuit is a large-scale-integrated peripheral device that executes the entire protocol of an automobile or industrial network.
Figure 3 Block Diagram
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Bus communication is based on the controller-area-network (CAN) protocol. With features like short message length, guaranteed reaction time for messages of appropriate priority, which is defined by the message identifiers. Also included are powerful error detection and treatment capabilities plus ease of operation. The CAN protocol is especially designed for the requirements of automobile and industrial electronic networks. The SFCAN circuit incorporates all the parts for completely independent transmission and reception of messages using the CAN protocol. The flexible, programmable interface allows connection to different implementations of the physical layer. The link to a host controller can be made either by a multiplexed 8-bit address/data bus or by a high-speed, serial synchronous interface. Message Memory The SFCAN circuit filters incoming messages with an associative memory (CAM = contentaddressable memory). For this the identifier and RTR bits of the required message must be written to the appropriate memory location. The identifier of each incoming message is compared with the identifiers stored in the CAM. Upon a match the received data bytes are written into the RAM buffer of the matching message. At the same time the corresponding receive-ready bit is set and a receive interrupt is generated, if it is enabled. If no match is detected, the received message is rejected. Identifiers can be reprogrammed at any time, although it is possible that data of the old or new identifier may be lost during reprogramming. An incoming transmit request will only be satisfied automatically by the hardware if the RTR bit of the particular identifier is set in CAM. To ensure data consistency when reading or writing several data bytes of a specific message the message objects are not accessed directly but via a 64-bit shadow register (see figure below). This shadow register stores the complete data field of a certain message object for both reading and writing. For read accesses the message's data field is copied to the shadow register... ...with the 1st read access to the respective data field (e.g. 80H ... 87H for message 0), or ...with any read access to byte 7 of the respective data field (e.g. 87H for message 0). This ensures that all bytes read via the shadow register belong to the same message, even though a new one might have been received in the meantime. For write accesses the shadow register is copied to the respective message data field... ...with any write access to byte 0 of the respective data field (e.g. 80H for message 0). This ensures that only completely updated message are transmitted. It is therefore recommended to begin all read and write accesses with the most-significant data byte of a message and end with data byte 0. This ensures operations on consistent data and correct transfers between the shadow register and the message RAM. Note: For these reasons it is absolutely essential to ensure that the writing of data is not interrupted by a read operation and vice versa, a read operation should not be interrupted by a write.
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Figure 4 CAM, Message Memory and Time-Stamp Registers
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Bit Stream Processor (BSP) The bit-stream processor controls the entire protocol, differentiates between the frames types and detects frame errors. Error Management Logic (EML) The error-management logic receives error messages from the BSP and, in turn, sends back information about error state to the BSP and CIL. Bit Timing Logic (BTL) The bit-timing logic determines the timing of the bits and synchronizes with the edges of the bit stream on the CAN bus. Transceiver Control Logic (TCL) The transceiver-control logic consists of programmable output driver, input comparator and input multiplexer. Clock Generator (CG) The clock generator consists of an oscillator and a programmable divider. The oscillator can be fed from an external quartz crystal, ceramic resonator or an external timing source. The permissible crystal frequency is 1 to 20 MHz, and the external clock may be between 0 and 20 MHz. A programmable frequency, dependent on the crystal clock, is available with the CLKOUT pin, e.g. for the clocking of a host controller. CPU Interface Logic (ClL) The CPU interface logic controls the access of the host via the parallel or serial interface, interprets the commands and outputs status and interrupt information. Transmit Check The CAN protocol ensures a very high integrity for the data transferred over the bus. The on-chip path from the data stored in parallel to the serial bit stream is not protected by the protocol. To eliminate any possible uncertainties at this point too, the SFCAN circuit incorporates a transmitcheck unit. This unit reads back a transmitted message via the normal receive path from the bus interface and compares the data with those written into the message memory by the host controller. If any inconsistency of the data is detected, the current message will be invalidated by an error frame. The transmit-check error counter TCEC is then incremented by 1. If this counter reaches 4 an error interrupt (bit TCI in the INT register) is generated, provided that this has not been masked (bit ETCI in the IMSK register). This count will also produce the Bus Off status. The TCEC is set to 0 after a reset and can be read and also written for test purposes at any time. Note: The transmit-check is an additional feature of the Siemens Full CAN Chip and is not part of the CAN protocol.
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Time Stamp It is impossible to determine from the received data in the message memory when they were received. So the host controller is unable to derive any information about the actuality or the repetition rate of the data. To enable an indication of the time of reception for at least some of the messages, a 16-bit timer is implemented on the SAE 81C90/91. The content of this gets written into the time-stamp registers of the particular message when it is received (for the messages 0 through 7). There are two timestamp bytes for each of the messages 0 through 7, and these hold the value of the 16-bit timer. The actuality of a message is determined by subtracting the old time-stamp of a message, stored in the host controller, from the new one, with respect to the timer overflow bit. Overflow of the timer can be detected by bit TSOV in the CTRL register. This bit does not trigger an interrupt and has to be reset by the host controller. Depending on the setting of bitfield TSP in register CTRL, the counter is fed with 1/32, 1/64, 1/128 or 1/256 of the bus clock. The momentary timer status can be read and set at any time. The timer starts at 0 after a reset and cannot be stopped. I/O-Ports There are two parallel I/O ports in the SAE 81C90, each with eight pins. These ports are configured pin by pin as input or output, depending on the contents of the port-direction register. The output data for the port pins can be written (latched) into the port-latch register. Reading this register reproduces the contents of the latch. The levels on the port pins can be read from the portpin register. For the SAE 81C91 in its P-LCC-28-1 package, the pads of the I/O ports are not bonded and therefore unavailable to the user. Note: Registers PxPDR and PxPL may be used for general purpose storage if the ports are not used.
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Device Control and Registers The operation of the SAE 81C90/91 is controlled via a number of registers. These registers allow initialization and function control, provide status information and configure the message objects. The upper part of the address space provides access to the data buffers of the message objects. The data buffers are ordered sequentially as shown in the table below. The register map on the next page summarizes the other registers (i.e. except the data registers) ordered by their address, while the following pages describe these registers in more detail from a functional point of view. Note: Locations marked "Reserved" in the register map must not be written in initialization mode. This also applies to locations 60H through 7FH. Data Registers Address 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H : F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH Function Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Byte 0 Byte 1 : Byte 6 Byte 7 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Message 15 : Message 14 Message 1 Message 0
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Register Map (ordered by address) Addr. 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Reg. Name Reset BL1 BL2 OC BRP RRR1 RRR2 RIMR1 RIMR2 TRS1 TRS2 IMSK 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Addr. 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Reg. Name Reset Addr. 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH Reg. Name Reset DR0H DR0L DR1H DR1L DR2H DR2L DR3H DR3L DR4H DR4L DR5H DR5L DR6H DR6L DR7H DR7L DR8H DR8L DR9H DR9L DR10H DR10L DR11H DR11L DR12H DR12L DR13H DR13L DR14H DR14L DR15H DR15L UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
P0PDR P0PR P0LR
----------------00H XXH 00H
Reserved Reserved Reserved Reserved Reserved
MOD INT CTRL
----------00H 00H 00H
Reserved
P1PDR P1PR P1LR
--00H XXH 00H
Reserved
TSR0H TSR0L TSR1H TSR1L TSR2H TSR2L TSR3H TSR3L TSR4H TSR4L TSR5H TSR5L TSR6H TSR6L TSR7H TSR7L
--UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH
Reserved
CC TCEC TCD
--01H 00H XXH
Reserved
TRR1 TRR2 RRP1 RRP2 TSCH TSCL
--00H 00H 00H 00H 00H 00H
Reserved Reserved
-----
Note: The locations marked "UUH" are not changed upon a reset. After a power on reset they are undefined (XXH), of course. Semiconductor Group 12
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Descriptor Registers A descriptor register is available for each message object and contains the eleven bits of the message identifier (ID.0 through ID.10), the remote-transmission-request bit (RTR) and the data length code (DLC) of a message. DRnH Address: XXH Reset Value: UUH DRnL Address: XXH Reset Value: UUH Bit(field) DLC 7 ID.10 rw 7 ID.2 rw 6 ID.9 rw 6 ID.1 rw 5 ID.8 rw 5 ID.0 rw 4 ID.7 rw 4 RTR rw rw rw 3 ID.6 rw 3 2 ID.5 rw 2 DLC rw rw 1 ID.4 rw 1 0 ID.3 rw 0
Function Data Length Code Defines the number of data bytes of message n. Defined values are 0000...1000, i.e. 0...8 bytes. Other values are not permitted. Remote Transmission Request Bit `0': This message operates as a data frame. `1': This message operates as a remote frame. Note: See description and table below. Identifier Identifier associated with message n, controls the acceptance of received frames and is inserted into transmitted frames.
RTR
ID.10-0
n = 0...15
Bit RTR determines the function of the corresponding message object when it is transmitted, and its reaction on a received data frame or remote frame. The table below summarizes the message object's behaviour in the different cases. RTR bit Object is transmitted '0' (data frame) The message object is transmitted as a standard data frame. Matching Data Frame received The data frame is stored in the message object. The data frame is ignored and not stored. Matching Remote Frame received The remote frame is ignored. The message object is sent as a data frame.
'1' The message object is (remote transmitted as a remote frame) frame (i.e. a request).
Note: For the transmission of remote frames (RTR = 1) the data-length-code should be set to `0'.
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Descriptor Register Arrangement Address 40H 41H 42H 43H : 5CH 5DH 5EH 5FH Function High Byte Low Byte High Byte Low Byte : High Byte Low Byte High Byte Low Byte Descriptor Register for Message Object 15 : Descriptor Register for Message Object 14 Descriptor Register for Message Object 1 Descriptor Register for Message Object 0
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Control Register Summary Register Name OC CC CTRL MOD INT IMSK BL1 BL2 BRP RRR1 RRR2 RIMR1 RIMR2 TRSR1 TRSR2 TRRR1 TRRR2 RRPR1 RRPR2 TSCH TSCL TCEC TCD P0PDR P1PDR P0LR P1LR P0PR P1PR Address 02H 14H 12H 10H 11H 0AH 00H 01H 03H 04H 05H 06H 07H 08H 09H 18H 19H 1AH 1BH 1CH 1DH 15H 16H 28H 2CH 2AH 2EH 29H 2DH Function Output-control register Clock-control register Control register Mode/status register Interrupt register Interrupt-mask register Bit-length register 1 Bit-length register 2 Baud-rate prescaler Receive-ready register 1 Receive-ready register 2 Receive-interrupt-mask register 1 Receive-interrupt-mask register 2 Transmit-request-set register 1 Transmit-request-set register 2 Transmit-request-reset register 1 Transmit-request-reset register 2 Remote-request-pending register 1 Remote-request-pending register 2 Time-Stamp counter high byte Time-Stamp counter low byte Transmit-check error counter Transmit-check data register Port 0 port-direction register Port 1 port-direction register Port 0 latch register Port 1 latch register Port 0 pin register Port 1 pin register Reset Value 00H 01H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H XX 00H 00H 00H 00H XXH XXH Read Write 1) r/w, I wo r/w r/w r/w r/w r/w, I r/w, I wo, I r/w r/w r/w r/w r/w r/w wo wo ro ro r/w r/w r/w ro r/w r/w r/w r/w ro ro
Note: 1) ro: read only, r/w: read and write access, wo: write only, I: access only with bit IM set.
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Output-Control Register The output drivers of the SAE 81C90/91's transmit pins (TXn) can be individually configured. Thus they can be adapted to the requirements of the external bs system.
OC Address: 02H Reset Value: 00H Bit(field) OCM
7 rw
6 rw
5 OCP1 rw
4 rw
3 rw
2 OCP0 rw
1 OCM rw
0 rw
OCTP1 OCTN1
OCTP0 OCTN0
Function Output Mode '0X': Normal Mode: '10': Test Mode: '11': Clock Mode: TX0 = Bit Sequence, TX0 = Bit Sequence, TX0 = Bit Sequence, TX1 = Bit Sequence. TX1 = RX0. TX1 = Bit Clock.
OCPn
Output Polarity '0': Output is driven directly with CAN data. '1': Output is driven with inverted CAN data. Negative Output Transistor Control '0': The low side output transistor TnN is disabled. '1': The low side output transistor TnN drives the pin according to data. Positive Output Transistor Control '0': The high side output transistor TnP is disabled. '1': The high side output transistor TnP drives the pin according to data.
OCTNn
OCTPn
n = 0, 1 Note: This register can only be written when bit IM (MOD.0) is set.
Figure 5 Output Control Circuitry
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Output Programming OCTP.n 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OCTN.n 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 OCP.n 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Data 0 = dominant 1 = recessive 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TnP OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON OFF OFF ON ON OFF TnN OFF OFF OFF OFF ON OFF OFF ON OFF OFF OFF OFF ON OFF OFF ON TXn-Level float float float float LOW float float LOW float HIGH HIGH float LOW HIGH HIGH LOW
TnP is the output transistor switching to VDD, TnN switches to VSS. TXn is the output level at the transmit pin. Clock Control Register The Clock Control Register determines the output frequency at pin CLKOUT which is derived from the oscillator frequency. CCR 7 6 5 4 3 2 1 0 Address: 14H CC Reset Value: 01H w w w w Bit(field) CC Function Clock Output Control '0000': fCLKOUT = fOSC '0001': fCLKOUT = fOSC / 2 '0010': fCLKOUT = fOSC / 4 '0011': fCLKOUT = fOSC / 6 '0100': fCLKOUT = fOSC / 8 '0101': fCLKOUT = fOSC / 10 '0110': fCLKOUT = fOSC / 12 '0111': fCLKOUT = fOSC / 14 '1XXX': fCLKOUT = LOW (clock output is switched off)
The Clock Control Register requires a special protocol for writing in order to prevent the clock output from being changed inadvertently: q Step 1: Write 80H to CC q Step 2: Write desired value to CC (bits 7...4 must be '0000') Note: Not defined bit positions must be '0' for write accesses. Semiconductor Group 17
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Control Register CTRL Address: 12H Reset Value: 00H 7 RX rw 6 TST rw rw 5 TSP rw 4 3 TSOV rw 2 SME rw 1 TCE rw 0 MM rw
Bit(field) MM
Function Monitor Mode '0': Message object 0 operates like all other objects. '1': Message object 0 receives all identifiers that are not accepted by other objects (corresponds to a Basic CAN receive register). Transmit Check Enable '0': If the transmit check detects an error, there is no intervention. '1': If the transmit check detects an error, the message is invalidated by an error frame and the error counter TCEC is incremented by 1. If the counter reaches 4, the Bus Off status is initiated and, if enabled, an interrupt (TCI) is generated. Sleep Mode Enable '0': Normal operation. '1': The sleep mode is enabled: the crystal oscillator is deactivated, all other activities are inhibited. The wake up is done by a reset signal or by an active signal at the CS pin or by an input edge going from recessive to dominant at pin Rx0 or Rx1. Time Stamp Overflow '0': There has been no overflow '1': There was at least one overflow of the time-stamp timer. Time Stamp Prescaler (Defines the input clock of the time-stamp timer) '00': fBL / 32 '01': fBL / 64 '10': fBL / 128 '11': fBL / 256 (For fBL see baud-rate prescaler BRP). Time Stamp Test '0': The prescaler is activated. '1': The time-stamp prescaler is deactivated. (Only for testing purposes, bit IM = MOD.0 must be set to '1'). Input Monitor RX This bit monitors the actual state of the digital input pin RX0.
TCE
SME
TSOV
TSP
TST
RX
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Mode/Status-Register
MOD Address: 10H Reset Value: 00H
7 ADE rw
6 RS r
5 TC r
4 TWL r
3 RWL r
2 BS r
1 RES rw
0 IM rw
Bit(field) IM
Function Init Mode '0': Normal mode. '1': Initialization mode: write access to the configuration registers BL1, BL2, OC, BRP is enabled. If the bit stays set, the chip enters the normal mode, with enabled access to the configuration registers. If this bit is set in conjunction with bit RES a hard software reset is activated. Reset Request '0': Normal mode. '1': The chip enters the reset state: - if bit IM = '0' a soft software reset takes place. - if bit IM = '1' a hard software reset takes place. Further details see below. Bus State (read only) '0': Normal mode. '1': Bus Off state, the IC does not participate in bus activities. Receiver Warning Level (read only) '0': Receive-error counter below 96. '1': Receive-error counter equal or above 96. Transmit Warning Level (read only) '0': Transmit-error counter below 96. '1': Transmit-error counter equal or above 96. Transmission Complete (read only) '0': The last transmission request is not yet executed successfully. '1': The last transmission request was executed successfully. Receive State (read only) '0': No reception active. '1': Currently the SAE 81C90/91 is in receive mode. Auto Decrement Enable '0': No automatic address decrement. '1': With every read or write access using the serial synchronous interface SI the address is automatically decremented by one. So data can be accessed sequentially without the need of writing a new address.
RES
BS
RWL
TWL
TC
RS
ADE
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Notes on Bit TC Scanning this bit is particularly useful if only one transmission is active. If there are several transmission jobs at the same time, it is better to scan the transmit-request register, because bit TC may possibly only be set very briefly between acknowledgment of the previous message and the start of the next one. Notes on Bit RES and IM and reset modes There are three different reset modes implemented in the SAE 81C90/91: hardware reset (activated by low level on pin RES) hard software reset (activated by setting both bits RES and IM to 1) soft software reset (activated by setting bit RES to 1 and bit IM to 0) The only difference between hardware and hard software reset affect bits RES and IM, that are not changed by software reset. With soft software reset the registers RRR1, RRR2, TRSR1, TRSR2, RRPR1 and RRPR2 are cleared, all bus activities are stopped, the error counters are not cleared, the Bus Off state is cancelled only after 128 idle phases (according to the CAN protocol 1 idle phase = 11 recessive bits in sequence). Simply spoken a soft software reset interrupts and cancels all bus activities and - if necessary - recovers from Bus Off state. Notes on Bit RS Bit RS directly reflects the internal status. RS is '0' during transmission or when the SAE 81C90/91 is idle. RS is '1' during reception or during the synchronization after a reset.
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Interrupt Register INT Address: 11H Reset Value: 00H 7 TCI rw 6 EPI rw 5 BOI rw 4 WUPI rw 3 RFI rw 2 WLI rw 1 TI rw 0 RI rw
Bit(field) RI
Function Receive Interrupt After a valid message has been received and filed, this bit is set and an interrupt generated. This bit will remain set until all bits of the registers RRR1 and RRR2 are reset. Transmit Interrupt This bit is set and an interrupt generated as soon as a transmit request has been processed. Warning Level Interrupt If at least one of the two error counters is greater than or equals 96, this bit is set and an interrupt generated. Remote Frame Interrupt This interrupt is generated after reception of a remote frame. Wake Up Interrupt After a wake-up this bit is set and an interrupt generated. Bus Off Interrupt This bit is set and an interrupt generated when the Bus Off status is entered. Error Passive Interrupt If at least one of the two error counters is greater than or equals 128, this bit is set and an interrupt generated. Transmit Check Interrupt If the transmit-check error counter reaches 4, this bit is set and an interrupt generated.
TI
WLI
RFI WUPI BOI EPI
TCI
Note: All bits of this register must be reset by software. This is done by writing '0' to the respective bit location, writing '1' has no effect. An interrupt is only generated if the respective IMSK bit is set. The bits in this register are set independent of register IMSK (see below). The interrupt output is active for at least one bit time. The interrupt output is deactivated when all enabled request bits are cleared. A request bit is enabled by setting its corresponding mask bit. Masked request bits do not activate the interrupt output.
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Interrupt-Mask Register These mask bits determine if an event activates the INT pin. They do not influence the INT register.
IMSK Address: 0AH Reset Value: 00H
7 ETCI rw
6 EEPI rw
5 EBOI rw
4 EWUPI rw
3 ERFI rw
2 EWLI rw
1 ETI rw
0 ERI rw
Bit(field) ERI
Function Enable Receive Interrupt '0': No receive interrupt enabled. '1': Receive interrupts are enabled. Enable Transmit Interrupt '0': No transmit interrupt enabled. '1': Completed transmit jobs generate interrupts. Enable Warning Level Interrupt '0': No warning level interrupt enabled. '1': There is an interrupt when the warning level is reached. Enable Remote Frame Interrupt '0': No remote frame interrupt enabled. '1': A receive interrupt is generated after receiving a remote frame Enable Wake Up Interrupt '0': No wake up interrupt enabled. '1': Wake-up interrupt is enabled. Enable Bus Off Interrupt '0': No bus off interrupt enabled. '1': Bus off interrupt is enabled. Enable Error Passive Interrupt '0': No error passive interrupt enabled. '1': Error passive interrupt is enabled. Enable Transmit Check Error Interrupt '0': No transmit check interrupt enabled. '1': Transmit-check error interrupt is enabled.
ETI
EWLI
ERFI
EWUPI
EBOI
EEPI
ETCI
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Bit-Length Registers
BL1 Address: 00H Reset Value: 00H Bit(field) TS1 TS2 SAM
7 SAM rw
6 rw
5 TS2 rw
4 rw
3 rw
2 TS1 rw
1 rw
0 rw
Function Length of Timing Segment 1 (TSeg1). tTSeg1 = (TS1 + 1) x tSCL. For tSCL see baud-rate prescaler BRP. Length of Timing Segment 2 (TSeg2).
tTSeg2 = (TS2 + 1) x tSCL. For tSCL see baud-rate prescaler BRP.
Sample Rate '0': Input signal is sampled once per bit. '1': Input signal is sampled three times per bit. Note: Bit SAM should only be set to '1' using very low baud rates.
BL2 Address: 01H Reset Value: 00H Bit(field) SJW SM
7 IPOL rw
6 DI rw
5 - -
4 - -
3 - -
2 SM rw
1 SJW rw
0 rw
Function Maximum Synchronization Jump Width. tSJWidth = (SJW + 1) x tSCL. For tSCL see baud-rate prescaler BRP. Speed Mode (Defines edge used for synchronization) '0': Recessive to dominant is used. '1': Both edges are used. Note: According to the CAN specification this bit should not be set to '1'. Digital Input '0': The input signal is applied to the input comparator. 1) '1': The input signal on pin RX0 is evaluated digitally. The input comparator is inactive. Pin RX1 should be on VSS. Input Polarity '0': The input level remains unaltered. '1': The input level is inverted.
DI
IPOL
Note: Not defined bit positions must be '0' for write accesses. The Bit Length Registers BL1 and BL2 can only written while bit IM (MOD.0) is set. 1) If the bus lines work according to the ISO specification, additional circuitry is necessary for interconnection of the input comparator to the bus lines.
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Baud Rate Prescaler Register The register is not readable and can only be written when bit IM (MOD.0) is set.
BRPR Address: 03H Reset Value: 00H Bit(field) BRP
7 - -
6 - -
5 w
4 w
3 BRP w
2 w
1 w
0 w
Function Baud Rate Prescaler This prescaler determines the period of the system clock: tSCL = (BRP + 1) x 2 x tOSC, where tOSC = 1 / fcrystal.
Note: Not defined bit positions must be '0' for write accesses.
The bit length tBL is computed as follows:
tBL = tTSeg1 + tTSeg2 + 1 tSCL
The baudrate BR can be computed with the following formula: BR = fcrystal / (2 x (BRP + 1) x (TS1 + TS2 + 3) ) Note: BRP TS1 TS2 see Baud Rate Prescaler Register see Bit Length Register 1 see Bit Length Register 1
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Receive-Ready Registers RRR2 Address: 05H Reset Value: 00H RRR1 Address: 04H Reset Value: 00H 7 RR15 rw 7 RR7 rw 6 RR14 rw 6 RR6 rw 5 RR13 rw 5 RR5 rw 4 RR12 rw 4 RR4 rw 3 RR11 rw 3 RR3 rw 2 RR10 rw 2 RR2 rw 1 RR9 rw 1 RR1 rw 0 RR8 rw 0 RR0 rw
Bit(field) RRn
Function Receive Ready Bit '0': No new message received in object n. '1': A new message has been received and stored in object n.
These register bits can be reset by writing '0' to the respective bit, writing '1' has no effect. Bit RRn is set when a message has arrived and been written into the memory location of message n. Setting this bit by hardware can generate a receive interrupt, which can be blocked by bit RIMn in the receive-interrupt-mask register. Bits RRn must be reset by software. Receive-Interrupt-Mask Registers Setting bit RIMn enables a receive interrupt to be generated if the receive-ready bit RRn has been set, i.e. a message has arrived and was written into the memory location of message n. RIMR2 Address: 07H Reset Value: 00H RIMR1 Address: 06H Reset Value: 00H 7 RIM15 rw 7 RIM7 rw 6 RIM14 rw 6 RIM6 rw 5 RIM13 rw 5 RIM5 rw 4 RIM12 rw 4 RIM4 rw 3 RIM11 rw 3 RIM3 rw 2 RIM10 rw 2 RIM2 rw 1 RIM9 rw 1 RIM1 rw 0 RIM8 rw 0 RIM0 rw
Bit(field) RIMn
Function Receive Interrupt Mask Bit '0': No interrupt upon reception of object n. '1': When a new message is stored in object n an interrupt is generated.
Note: Bit ERI in the interrupt-mask register IM blocks all receive interrupts, even if bits RIMn are set.
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Transmit Request Registers The Transmit Request Set Registers provide a transmission request bit (TRSn) for each message object. Setting a transmission request bit causes the respective message x to be transmitted. The bit is cleared by hardware after transmission. Several bits can be set simultaneously. In this way all messages whose request bits are set are transmitted in turn, starting with the memory location with the highest number. Note: A transmission request bit is set by writing '1' to the respective bit location (TRSn). Writing '0' has no effect.
TRSR2 Address: 09H Reset Value: 00H TRSR1 Address: 08H Reset Value: 00H
7 TRS15 rw 7 TRS7 rw
6 TRS14 rw 6 TRS6 rw
5 TRS13 rw 5 TRS5 rw
4 TRS12 rw 4 TRS4 rw
3 TRS11 rw 3 TRS3 rw
2 TRS10 rw 2 TRS2 rw
1 TRS9 rw 1 TRS1 rw
0 TRS8 rw 0 TRS0 rw
Bit(field) TRSn
Function Transmit Request Set Bit '0': No change of the respective transmit request bit. '1': The respective transmit request bit is cleared.
n = 0...15
The Transmit Request Reset Registers provide a transmit request reset bit (TRRn) for each transmit request bit TRSn, i.e. for each message object. Writing '1' to a TRRn bit clears the corresponding transmission request bit TRSn. This causes a transmission request, initiated by the corresponding bit TRSn, to be cancelled, provided that it is not currently processed. This scheme avoids conflicts when writing to register bits while they are cleared by hardware because of a completed transmission. Note: Registers TRRRx cannot be read.
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TRRR2 Address: 19H Reset Value: 00H TRRR1 Address: 18H Reset Value: 00H
7 TRR15 w 7 TRR7 w
6 TRR14 w 6 TRR6 w
5 TRR13 w 5 TRR5 w
4 TRR12 w 4 TRR4 w
3 TRR11 w 3 TRR3 w
2 TRR10 w 2 TRR2 w
1 TRR9 w 1 TRR1 w
0 TRR8 w 0 TRR0 w
Bit(field) TRRx
Function Transmit Request Reset Bit '0': No change of the respective transmit request bit. '1': The respective transmit request bit is cleared.
Remote-Request-Pending Registers RRPR2 Address: 1BH Reset Value: 00H RRPR1 Address: 1AH Reset Value: 00H 7 RRP15 r 7 RRP7 r 6 RRP14 r 6 RRP6 r 5 RRP13 r 5 RRP5 r 4 RRP12 r 4 RRP4 r 3 RRP11 r 3 RRP3 r 2 RRP10 r 2 RRP2 r 1 RRP9 r 1 RRP1 r 0 RRP8 r 0 RRP0 r
Bit(field) RRPn
Function Remote Request Pending Bit '0': No remote request pending. '1': A remote request (remote frame) for message n was received but is not yet answered by the transmission of the corresponding data frame.
n = 0...15
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Message Time Stamp This mechanism stores the time at which a specific message was received, i.e. it assigns a time stamp to that message. For this purpose the contents of the free-running time stamp counter TSC is copied to the time stamp register TSRn of the respective message object upon reception of this message.
The Time Stamp Counter Registers provide access to the free-running time stamp counter. TSCH Address: 1CH Reset Value: 00H TSCL Address: 1DH Reset Value: 00H Bit(field) TSC 7 rw 7 TSC.7 rw 6 rw 6 TSC.6 rw 5 rw 5 TSC.5 rw 4 rw 4 TSC.4 rw 3 rw 3 TSC.3 rw 2 rw 2 TSC.2 rw 1 TSC.9 rw 1 TSC.1 rw 0 TSC.8 rw 0 TSC.0 rw
TSC.15 TSC.14 TSC.13 TSC.12 TSC.11 TSC.10
Function Time Stamp Counter Current contents of the free running time stamp counter.
The Time-Stamp Registers are available for each of message objects 0...7 (see table below) and contain the time-stamp of the corresponding message. These registers can only be read. TSRnH Address: 3XH Reset Value: UUH TSRnL Address: 3XH Reset Value: UUH Bit(field) TSn 7 TSn.15 r 7 TSn.7 r 6 TSn.14 r 6 TSn.6 r 5 TSn.13 r 5 TSn.5 r 4 TSn.12 r 4 TSn.4 r 3 TSn.11 r 3 TSn.3 r 2 TSn.10 r 2 TSn.2 r 1 TSn.9 r 1 TSn.1 r 0 TSn.8 r 0 TSn.0 r
Function Time Stamp n A 16-bit timer value to identify the time of reception of message n.
n = 0...7
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Time Stamp Register Table Address 30H 31H 32H 33H : 3CH 3DH 3EH 3FH Function High Byte Low Byte High Byte Low Byte : High Byte Low Byte High Byte Low Byte Time-Stamp 7 : Time-Stamp 6 Time-Stamp 1 Time-Stamp 0
Transmit Check Error Counter TCEC Address: 15H Reset Value: 00H Bit(field) TCECV 7 6 5 4 3 rw 2 1 TCECV rw rw 0
Function Transmit Check Error Counter Value Number of errors detected by the transmit check unit. When a count of 4 is reached an interrupt is generated if enabled. If bit TCE (CTRL.1) is set to '1' the Bus Off status is entered in this case.
Note: Not defined bit positions must be '0' for write accesses. Transmit Check Data Register This register supports an error analysis when a transmit check error is encountered. Reading TCD provides the byte which was actually being sent when the error occurred. TCD Address: 16H Reset Value: XXH Bit(field) Data Byte r r r 7 6 5 4 r 3 r 2 r 1 r 0 r
Data Byte
Function The data byte which was attempted to be sent while a transmit check error was encountered.
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Port Control Registers These registers control the parallel ports P0 and P1 which are provided in the SAE 81C90.
The Port Direction Registers PxPDR select each port pin separately for input (PxPDR.n='0') or output (PxPDR.n='1'). After reset the ports are switched as inputs. P1PDR Address: 2CH Reset Value: 00H P0PDR Address: 28H Reset Value: 00H 7 rw 7 rw 6 rw 6 rw 5 rw 5 rw 4 rw 4 rw 3 rw 3 rw 2 rw 2 rw 1 rw 1 rw 0 rw 0 rw
P1PD.7 P1PD.6 P1PD.5 P1PD.4 P1PD.3 P1PD.2 P1PD.1 P1PD.0
P0PD.7 P0PD.6 P0PD.5 P0PD.4 P0PD.3 P0PD.2 P0PD.1 P0PD.0
The Port Latch Registers PxLR store the output data for those port pins that are switched to output. P1LR Address: 2EH Reset Value: 00H P0LR Address: 2AH Reset Value: 00H 7 P1L.7 rw 7 P0L.7 rw 6 P1L.6 rw 6 P0L.6 rw 5 P1L.5 rw 5 P0L.5 rw 4 P1L.4 rw 4 P0L.4 rw 3 P1L.3 rw 3 P0L.3 rw 2 P1L.2 rw 2 P0L.2 rw 1 P1L.1 rw 1 P0L.1 rw 0 P1L.0 rw 0 P0L.0 rw
The Port Pin Registers PxPR provide the current level of the port pins. These registers can only be read. P1PR Address: 2DH Reset Value: 00H P0PR Address: 29H Reset Value: 00H 7 P1P.7 r 7 P0P.7 r 6 P1P.6 r 6 P0P.6 r 5 P1P.5 r 5 P0P.5 r 4 P1P.4 r 4 P0P.4 r 3 P1P.3 r 3 P0P.3 r 2 P1P.2 r 2 P0P.2 r 1 P1P.1 r 1 P0P.1 r 0 P1P.0 r 0 P0P.0 r
In parallel to the standard CMOS structure there are additional internal pullup devices of about 10...200 k at each port pin. Note: Registers PxPDR and PxPL may be used for general purpose storage if the ports are not used.
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07Feb95@09:05h Intermediate Version
SAE 81C90/91
Bit Timing A regular bit period is composed of the following three segments:
q synchronization segment q timing segment 1 q timing segment 2.
The sampling point is between timing segment 1 and timing segment 2.
Figure 6 Bit Time Segments Synchronization The edge of the input signal is expected during the sync segment (duration = 1 system clock cycle = 1 tSCL). Timing Segment 1 (TSeg1) Timing segment 1 determines the sampling point within a bit period. This point is always at the end of segment 1. The segment is programmable from 1 to 16 tSCL (see bit-length register BL1). Timing Segment 2 (TSeg2) Timing segment 2 provides extra time for internal processing after the sampling point. The segment is programmable from 1 to 8 tSCL (see bit-length register BL1). Synchronization Jump Width (SJW) To compensate for phase shifts between the oscillator frequencies of the different bus stations, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. The synchronization jump width (SJW) determines the maximum number of system clock pulses by which the bit period can be lengthened or shortened for resynchronization. The synchronization jump width is programmable from 1 to 4 tSCL (see bit-length register BL2).
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Figure 7 Lengthening a Bit Period
Figure 8 Shortening a Bit Period Delay Times The total delay is calculated from the following single delays:
q q q q
2 x physical bus tBus (max. 100 ns acc. to CAN specification) 2 x input comparator tComp (depends on application circuit) 2 x output driver tDriver (depends on application circuit) 1 x input to output of CAN controller tInOut (max. 1 tSCL + 80 ns)
tDelay = 2 x (tBus + tComp + tDriver) + tInOut
Recommendations On the premise of the stated conditions, there are the following essential requirements to be maintained:
tTSeg1 tTSeg1 tTSeg2 tTSeg2
>
tSeg2 tDelay tSJW 3 x tSCL + tSJW
if bit SAM = 1 (otherwise bit recognition does not work).
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Host Interfaces There are two different host interfaces implemented in the SAE 81C90/91. Data and addresses on a multiplexed 8-bit bus, compatible with Siemens microcontrollers (C5xx, C16x), can be transferred via the parallel interface (PI). Using the serial synchronous interface (Sl), any host controller with a serial three-lead interface can be connected with. The interface is selected by hardware through the wiring of the MS (Mode Select) pin. This pin may not be switched during operation. If there is a High level on the MS pin, the SI and thus pins DI, DO, CLK, W and TIM are activated, while pins AD5 through AD7, RD, WR and ALE are inactive. A Low level on the MS pin switches to the Pl and thus activates pins AD0 through AD7, RD, WR and ALE. Parallel Interface Pl The parallel interface uses a multiplexed 8-bit address/data bus. First the address of the required register is applied to the pins AD0 through AD7. A falling edge on pin ALE means that this address is transferred to an on-chip latch. After this, data can either be written into the selected register (pin WR = 0) or read from it (pin RD = 0) via the address/data bus. Pin CS must be 0 for the entire duration of the RD/WR active time so that the circuit is activated. Serial Synchronous Interface Sl If the SI is used the unused pins of PI must be set to inactive levels (RD, WR to VDD and ALE, AD5, AD6, AD7 to VSS). Communication on the SI is accomplished according to the following procedure: Each access to the stand-alone Full-CAN circuit has to be started by activating the device (CS = 0). After the beginning of access, an address must be written first and then data can be read or written. The required function is determined by pin W (W = 1: read; W = 0: write). If the automatic decrementing of the address is activated (bit ADE in the MOD register), any number of data bytes can be accessed in succession. Finally the device has to be deactivated. Procedure:
q q q q q
Activate device (CS = 0) Set pin W to 1 for read, to 0 for write Write in address of first data byte Read out/write in one or more data bytes Deactivate device (CS = 1)
The most-significant bit is always output as the first bit of an address or a data byte. Data from pin DI are transferred into the internal shift register with the rising edge of the clock. The active clock edge of pin DO is selectable via the pin TIM. If this pin is 0 the data are output from the shift register to pin DO with the rising clock edge (Timing A). If the pin TIM is 1, the output of data is done with the falling edge (Timing B). The timing for reading and writing of two data bytes with automatic decrementing activated is illustrated below.
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Figure 9 Serial Interface Timing (for 2 Data Bytes)
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Absolute Maximum Ratings Ambient temperature under bias (TA): ..................................................................... - 40 to + 110 C Storage temperature (TST)........................................................................................ - 50 to + 150 C Voltage on VCC pins with respect to ground (VSS) ..................................................... - 0.5 to + 6.0 V Voltage on any pin with respect to ground (VSS) .................................................- 0.5 to VCC + 0.5 V Input current on any pin during overload condition .................................................. - 10 to + 10 mA Absolute sum of all input currents during overload condition ............................................. |100 mA| Power dissipation..................................................................................................................... 0.5 W
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the voltage on pins with respect to ground (VSS) must not exceed the values defined by the Absolute Maximum Ratings.
Parameter Interpretation The parameters listed in the following partly represent the characteristics of the SAE 81C90/91 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": DC (Device Characteristics): The logic of the SAE 81C90/91 will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the SAE 81C90/91.
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DC Characteristics VCC = 5 V 10 %; VSS = 0 V TA = - 40 to + 110 C Parameter Input low voltage (all except XTAL1 and XTAL2) Input low voltage (XTAL1 and XTAL2) Input high voltage (all except XTAL1 and XTAL2) Input high voltage (XTAL1 and XTAL2) Comparator input voltage 1) Common mode voltage Hysteresis 2) Offset voltage 2) Output low voltage (all except CLKOUT, TX0, TX1) Output low voltage (CLKOUT) Output high voltage (all except CLKOUT, TX0, TX1) Output high voltage (CLKOUT) Input leakage current Source output current (TX0, TX1) Sink output current (TX0, TX1) Low end capacitance 5)
2) 2)
Symbol min.
Limit Values max. 0.3 VCC 0.5
Unit V V V V V V mV mV V V V V A mA mA pF pF mA
Test Condition - - - - - - - -
VIL
SR 0
VILX SR 0 VIH
SR 0.7 VCC
VCC VCC VCC + 0.5 VCC - 1.5
100 3) 100 3) 0.2 VCC 0.4
VIHX SR VCC - 1.0 VCI
SR 0.5
VICOM SR 1.5 VHYS DC - VOFF DC - VOL DC - VOLC DC - VOH DC 0.8 VCC VOHC DC VCC - 0.8 II
DC -
IOL = 1.6 mA IOL1 = 10 mA IOH = - 1.6 mA IOH = - 10 mA
0 V < VIN < VCC 4)
VCC VCC
1 - - 12 10 30
ISRC DC 5 ISNK DC 5 CL CI ICC
DC 6.8 DC - -
VO = VCC - 1 V VO = 1 V f = 1 MHz TA = 25 C
Pin capacitance
Power supply current
Notes
1) 2) 3) 4) 5)
If the bus lines work according to the ISO specification, additional circuitry is necessary for interconnection of the input comparator to the bus lines. Not 100% tested, guaranteed by design characterization. This value is a typical value! This specification does not apply to the port pins (P00...P07, P10...P17) due to the implemented pullups! In oscillator mode the size of the low-end capacitance must correspond to the specification of the crystal manufacturer. The optimum values depend on the selected crystal, the intended frequency and the actual application hardware (stray capacitances). 10 pF are recommended for CL. For best results keep the crystal circuitry connections as short as possible and keep the CLKOUT line away from it. If the CLKOUT signal is not required by the system it should be switched off.
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AC Characteristics (General Timing)
VCC = 5 V 10 %; VSS = 0 V TA = - 40 to + 110 C
Parameter Oscillator period Clock input high time Clock input low time Reset pulse width Output rise time 1) Output fall time 1) CLKOUT rise time
1)
Symbol
Limit Values min. max. - - - 40 40 20 20
Unit ns ns ns
Test Conditions
tOSC SR 50 tH tL tQR tQF
SR 23.5 SR 23.5 DC - DC -
tRES SR 2
tOSC
ns ns ns ns CL = 70 pF CL = 70 pF CL = 50 pF CL = 50 pF
tQRC DC - tQFC DC -
CLKOUT fall time 1)
1)
Not 100% tested, guaranteed by design characterization.
AC Characteristics (SI Timing)
VCC = 5 V 10 %; TA = - 40 to + 110 C;
Parameter Chip Select Setup Clock High Time Clock Low Time Clock Period DI Setup DI Hold Address to Data Out Output Delay Data Float after CS high Chip Select Hold Write to Clock W to CS high Address to Data In
VSS = 0 V CL = 50 pF
Symbol Limit Values min. max. ns ns ns ns ns ns ns 25 25 0 DC 0 ns ns ns ns ns ns Unit Test Conditions
tCSS SR 10 tCH tCL tC tDIS tDIH tOD tDF tWC tADI
SR 1.5 tOSC + 10 SR 1.5 tOSC + 10 SR 4 tOSC SR 10 SR 0 DC DC
tADO DC 3 tOSC
tCSH SR 1 tOSC tWCS SR 0
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Figure 10 SI-Read-Timing (Timing A: Pin TIM = 0)
Figure 11 SI-Read-Timing (Timing B: Pin TIM =1)
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Figure 12 SI-Write-Timing AC Characteristics (PI Timing) VCC = 5 V 10 %; VSS = 0 V TA = - 40 to + 110 C; CL = 50 pF Parameter Read-Cycle time Write-Cycle time ALE pulse width Address setup to ALE low Address hold after ALE low RD pulse width WR pulse width ALE low to WR active ALE low to RD active Data float after RD high RD low to data valid Data setup before WR high Data hold after WR high CS low to RD low CS low to WR low WR high to next ALE low Symbol min. Limit Values max. ns ns ns ns ns ns ns ns ns 20 2 tOSC + 20 ns ns ns ns ns ns ns Unit Test Condition
tCYR DC 4 tOSC tCYW DC 4 tOSC tLHLL DC 30 tAVLL SR 10 tLLAX SR 10 tRLRH SR 2 tOSC + 30 tWLWH SR 2 tOSC + 30 tLLWL SR 20 tLLRL SR 20 tRFDX DC 0 tRLDV DC tDVWH SR 10 tWHDX SR 5 tCLRL / SR 0 tCLWL SR 0 tWHLL SR 1.5 tOSC
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Figure 13 PI Timing: Read-Cycle-Timing
Figure 14 PI Timing: Write-Cycle-Timing
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